O circuito lógico TTL é um dispositivo TTL que possui quatro portas lógicas AND de duas entradas cada porta. Ele é usado, principalmente, em circuitos. jpg ( × pixels, file size: 15 KB, MIME type: image/jpeg). Open in Media English: chip Date, 14 Circuito integrado Utilice dos CI y un CI Contador decimal Esto se hace iniciando el circuito con cada uno de los seis estados no utilizados mediante las entradas de .

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Circuito integrado – EcuRed

For a more detailed analysis or checking the effect in the ventilation circuit due to mining changes, computational simulation can be used. Copper has 20 orbiting electrons with only one electron in the outermost shell. This is probably the largest deviation to be tolerated.

As I B increases, so does I C. Network redrawn to determine the Thevenin equivalent: Thus, the design is relatively stable in regard to any Beta variation. IF as shown in Fig. The experimental data is equal to that obtained from the simulation. The dc collector voltage of stage 1 determines the dc base voltage of stage 2. LED-Zener diode combination b. Not in preferred firing area.

The logic states of the simulation and those experimentally determined are identical. Yes Transient Analysis 1.


Therefore, a plot of IC vs. For either Q1 or Q2: Log In Sign Up.

This is a logical inversion of the OR gate. Computer Analysis PSpice Simulation 1. The larger the magnitude of the applied gate-to-source voltage, the larger the available channel.


For voltage divider-bias-line see Fig. The heavy doping greatly reduces the width of the depletion region resulting in lower levels of Zener voltage.

The Beta of the transistor is increasing.

Considerably less for the voltage-divider configuration compared to the other three. The experimental data is identical to that obtained from the simulation. The important voltage VCEQ was measured at 8.

The circuitp delay measured was about 13 nanoseconds.

Clampers R, C, Diode Combination b. The variations for Alpha and Beta for the tested transistor are not really significant, resulting in an almost ideal current source which is independent of the voltage VCE. VT Vdc 2V No significant discrepancies 8. Zener Diode Characteristics b. Y is identical to that of the TTL clock.

An n-type semiconductor material has an excess of electrons for conduction established by doping an intrinsic material with donor atoms having more valence electrons than needed to establish the covalent bonding. See circuitl diagrams above.

Filejpg – Wikimedia Commons

The voltage level of the U1A: It rises exponentially toward its final value of 2 V. We note that the voltages VC1 and VB2 are not the same as they would be if the voltage across capacitor CC was 0 Volts, indicating a short circuit across that capacitor. In a complex ventilation layout these techniques proved to be extreme laborious.


Their shapes are similar, but for a given ID, the potential VD is greater for the silicon diode compared to the germanium diode. Common-Base DC Bias a. The maximum level of I Rs will in turn determine the maximum permissible level of Vi.

That measurement which is closest to that of the counter is the better measurement. In the case of the 2N transistor, which had a higher Beta than the 2N transistor, the Q point of the former shifted higher up the fircuito toward saturation.

B are the 74008 to the gate, U1A: Therefore, in relationship to the existing resistors in the circuit, it circkito be neglected without making a serious error.

Computer Exercises PSpice simulation 1. The frequency at the U1A: Collector Feedback Configuration with RE a. This is a generally well known factor. The greatest rate of increase in power will occur at low illumination levels. PSpice Simulation Part A 4. High Frequency Response Calculations a. Example of a calculation: